1. Field of the Invention
The present invention relates to a semiconductor device with an SOI (semiconductor-on-insulator) structure.
2. Description of the Background Art
A well-known semiconductor device with an SOI structure comprises a BOX (buried oxide) layer provided on a silicon substrate, and a semiconductor layer provided on the BOX layer. As an example of a diode which is formed in the semiconductor layer on the BOX layer, a PiN diode structure is generally known which includes a P-type region as an anode, an N+-type region as a cathode, and an N−-type region between the P-type region and the N+-type region. An exemplary structure of which is introduced in Japanese Patent Application Laid-Open No. 6-188438 (1994) or U.S. Pat. No. 5,485,030. As a precondition for improving a breakdown voltage of a diode having such a structure, even when the N−-type region is in a completely depleted state, avalanche breakdown should be prevented in an area of an element having a maximum electric field.
When such a diode is brought to a state in which the P-type region (anode) and the silicon substrate are at 0 V, and a positive voltage is applied to the N+-type region (cathode) (which state will be referred to as a “reverse-biased state”), a depletion layer at pn junction between the P-type region and the N−-type region is caused to extend, entering into the N−-type region. Supposing that the anode and the cathode are spaced with a sufficient distance therebetween, the silicon substrate under the BOX layer is operative to serve as a field plate, thereby causing a depletion layer at a boundary between the N−-type region and the BOX layer to extend, further entering into the N−-type region. The extension of the latter depletion layer facilitates the extension of the former depletion layer. As a result, an electric field is relaxed at the pn junction between the N−-type region and the P-type region, which effect is generally called as RESURF (reduced surface field) effect. The conditions for the depletion layer to extend from the boundary between the N−-type region and the BOX layer into the N−-type region are called as RESURF conditions.
When the RESURF conditions are satisfied, localized concentration of an electric field is relaxed in an active layer, whereby the electric field exhibits a distribution suitable for improving a breakdown voltage. In this case, the diode bears a breakdown voltage which depends on avalanche breakdown occurring at an interface between the N−-type region and the BOX layer, in an area directly below the N+-type region. That is, the breakdown voltage of the diode is determined by the sum of voltage drops caused by the electric field in the N−-type region and the BOX layer, in the region directly below the N+-type region. Especially, the BOX layer experiences an extremely large voltage drop, significantly exerting an influence on the breakdown voltage of the diode as a whole. In response, as a way to obtain a high breakdown voltage of a semiconductor device as disclosed in Japanese Patent Application Laid-Open No. 6-188438 (1994) or U.S. Pat. No. 5,485,030, the present inventor has suggested increase in thickness of the BOX film, or provision of a region in the BOX layer having a low dielectric constant such as a vacuum layer.
Increase in thickness of the BOX layer may be the most realistic way to provide a high breakdown voltage of a semiconductor device. On the other hand, it will be harder to obtain RESURF effect as the BOX layer increases in thickness, causing difficulty in bringing a bottom part of the N−-type region on the side of the anode to a depleted state. In order to obtain a high breakdown voltage of 1000 V or more, the BOX layer should be 6 μm or more in thickness. In terms of manufacturing process and manufacturing efficiency, however, the maximum possible thickness of the BOX layer is around 4 μm.
As another way to improve a breakdown voltage of a semiconductor element, provision of surface asperities to the BOX layer, or provision of a floating electrode within the BOX layer, has been suggested. An exemplary technique of which is introduced in Japanese Patent Application Laid-Open No. 8-88377(1996).
As still another way to improve a breakdown voltage of a semiconductor device, an SIPOS (semi-insulating polysilicon) layer may be provided to the bottom part of the N−-type region, an exemplary technique of which is introduced in “New 1200 V MOSFET Structure on SOI with SIPOS Shielding Layer”, Proceedings of 1998 International Symposium on Power Semiconductor Devices & ICs, pp. 25-28. The SIPOS layer has a high resistance capable of controlling a mobility of electric charges therein to a minimum possible degree. The SIPOS layer is charged according to the electric field applied thereto, is operative to shield the electric field. Further, the SIPOS layer has such a distribution of electric charges that the strength of the electric field applied thereto is weakened. Due to the low mobility of electric charges, electric charges induced into the SIPOS layer are hard to provide such an energy level that an avalanche phenomenon occurs.
In a diode including the SIPOS layer, electric field concentration in the N−-type region is relaxed, eventually producing an approximately uniform electric field distribution that is similar to the distribution obtained by a one-dimensional PiN diode. At this time, in the area directly below the N+-type region, electric field is generated mostly in the BOX layer. That is, in the area directly below the N+-type region, voltage drop occurs mostly in the BOX layer. As a result, the diode including the SIPOS layer is theoretically allowed to have a breakdown voltage of up to the breakdown voltage of the BOX layer.
As discussed, increase in thickness of the BOX may be the most realistic way for improving a breakdown voltage of a semiconductor device with an SOI structure, on which constraints are imposed by manufacturing process and manufacturing efficiency.
As discussed, surface asperities may be provided to the BOX layer as taught by Japanese Patent Application Laid-Open No. 8-88377 (1996). When a diode provided on this BOX layer is brought to a reverse-biased state, an inversion layer is formed at recesses of the surface asperities of the BOX layer for weakening the electric field strength of a semiconductor element. This develops a strong electric field around the bottom surface of a semiconductor layer including the diode formed therein, possibly producing a transient avalanche phenomenon at the interface between the semiconductor layer and the BOX layer thereunder. Such a phenomenon leads to an initial leakage current or variation in breakdown voltage. For this reason, the semiconductor element provided with surface asperities on the BOX layer is unsuitable for maintaining a dynamic voltage level. The BOX layer may alternatively be provided with a floating electrode, in which case this floating electrode should be charged by applying a high voltage to the semiconductor device in advance to produce an avalanche phenomenon.
Still as discussed, provision of an SIPOS film over the BOX layer also leads to improvement in breakdown voltage of a semiconductor device. In contrast to a single crystal, however, carriers of the SIPOS film are generally at an intermediate energy level, which fact causes carrier excitation. As a semiconductor element rises in temperature, the SIPOS film decreases in resistivity, leading to a heavy loss of energy caused by a leakage current. This means that a tolerance to high temperature, as one of the great advantages of an SOI structure, suffers restraints. In addition, the SIPOS film provides a low carrier mobility, disadvantageously affecting transient response characteristic. That is, speed of polarization cannot be responsive to voltage application.